FIG. 1 depicts a block diagram of a multi-processor and a multi-port memory. In general, the fact that the multi-processor comprises a plurality of execution units causes it to actually or virtually access more than one word within the memory at a time. There are three well-known memory architectures in the prior art for doing so.
In accordance with the first architecture, a full N-port design is employed that allows any N memory locations to be accessed from any port without blocking. The full N-port design is the fastest of the multi-port architectures, but is also the largest.
In accordance with the second architecture, a single-port memory with contention resolution is employed that functions as a single-server, multi-queue system. The single-port memory with contention resolution is the slowest of the multi-port architectures, but is also the smallest.
In accordance with the third architecture, a plurality of independent memory banks with contention resolution are employed. So long as each processor seeks data in a different memory bank, there is no contention. In contrast, when two processors seek data in the same memory bank, there is contention and one of them has to wait. An advantage of the third architecture is that its speed and size are a function of the number of memory banks used, and, therefore, its space-time parameters can be tailored for the application. For example, when the third architecture has a large number of memory banks, its speed and size approach that of the full N-port design, but when the third architecture has only 2 memory banks, it's speed and size approach that of the single-port memory.
FIG. 2 depicts a graph of the space-time parameters for three multi-port architectures in the prior art.
Although the three principal architectures provide a variety of space-time parameters, there are special-purpose applications that need a multi-port architecture with better space-time parameters than are exhibited by architectures in the prior art.